NDLI: Breaking the memory bottleneck with an optical data path

Content Provider	IEEE Xplore Digital Library
Author	Fritts, J.E. Chamberlain, R.D.
Copyright Year	2002
Description	Author affiliation: Comput. & Commun. Res. Center, Washington Univ., St. Louis, MO, USA (Fritts, J.E.; Chamberlain, R.D.)
Abstract	We demonstrate the capability of optical buses in enabling orders of magnitude greater bandwidth between the processor and off-chip memory in a uniprocessor computer system. Through a simulation-based performance analysis of a 1 GHz processor model, we provide a preliminary evaluation of the benefits of an optical processor-to-memory bus in both eliminating the bandwidth bottleneck and in reducing the impact of the increasing processor-to-memory latency gap. The optical technology is constructed of two-dimensional arrays of lasers and detectors bonded to silicon that provide high-speed optical I/O on and off chip. These chip-to-chip light paths may be designed using either rigid free-space optics or flexible fiber image guides. Utilizing the optical data path between the processor and memory provides significantly greater bandwidth with no appreciable latency penalty. We assess the performance impact of this architecture enhancement on a number of media applications. Overall we found that the increased bandwidth nearly eliminates the transfer time between processor and memory, effectively reducing degradation from off-chip memory latency by 50% on average. Additionally, substantial extra bandwidth remains for more bandwidth-intensive architectural options like aggressive latency hiding techniques and single-chip multiprocessors.
Sponsorship	Soc. Comput. Simulation Int
Starting Page	352
Ending Page	362
File Size	400913
Page Count	11
File Format	PDF
ISBN	0769515525
ISSN	1082241X
DOI	10.1109/SIMSYM.2002.1000173
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2002-04-14
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	High speed optical techniques Bandwidth Delay Optical arrays Optical computing Computational modeling Analytical models Performance analysis Sensor arrays Fiber lasers
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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