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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Hyungwook Park Fishwick, P.A. |
| Copyright Year | 2008 |
| Description | Author affiliation: Dept. of Comput. & Inf. Sci. & Eng., Univ. of Florida, Gainesville, FL, USA (Hyungwook Park; Fishwick, P.A.) |
| Abstract | The trend in computing architectures has been toward multi-core central processing units (CPUs) and graphics processing units (GPUs). An affordable and highly parallelizable GPU is practical example of Single Instruction, Multiple Data (SIMD) architectures oriented toward stream processing. While the GPU architectures and languages are fairly easily employed for inherently time-synchronous based simulation models, it is less clear if or how one might employ them for queuing model simulation, which has an asynchronous behavior. We have derived a two-step process that allows SIMD-style simulation on queuing networks, by initially performing SIMD computation over a cluster and following this research with a GPU experiment. The two-step process simulates approximate time events synchronously and then reduces the error in output statistics by compensating for it based on error analysis trends. We present our findings to show that, while the outputs are approximate, one may obtain reasonably accurate summary statistics quickly. |
| Starting Page | 795 |
| Ending Page | 803 |
| File Size | 298142 |
| Page Count | 9 |
| File Format | |
| ISBN | 9781424427079 |
| DOI | 10.1109/WSC.2008.4736142 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2008-12-07 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Discrete event simulation Computational modeling Computer architecture Error analysis Central Processing Unit Graphics Computer networks Analytical models Statistical analysis Statistics |
| Content Type | Text |
| Resource Type | Article |
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