NDLI: Operational simulation of an X-ray lithography cell: comparison of 200 mm and 300 mm wafers

Content Provider	IEEE Xplore Digital Library
Author	White Jr., K.P. Trybula, W.J.
Copyright Year	1999
Description	Author affiliation: Dept. of Syst. Eng., Virginia Univ., Charlottesville, VA, USA (White, K.P., Jr.)
Abstract	We review progress on a project to evaluate prospective operations in a semiconductor wafer fab that employs next generation, proximity X-ray lithography to pattern the critical dimensions of computer chips. A simulation model is developed that captures the processing of wafers through an X-ray lithography cell using a synchrotron as the source of exposure radiation. The model incorporates the best current information on unit-cell design and processing times and implements a range of events that interrupt the flow of wafers processing on the cell. Performance measures estimated from the simulation include the weekly throughput for the cell and the frequency of SEMI E-10 equipment states for the corresponding exposure tool. Simulation experiments are conducted to compare the performance of a cell fabricating 200 mm wafers with that of a cell fabricating 300 mm wafers, for each of three different chip sizes. Results illustrate the anticipated dependence of average wafer throughput on wafer size and assumptions regarding the number of chips per wafer, with a maximum of approximately 3400 wafers/week for 200 mm wafers with 25/spl times/25 mm field size. Ignoring wafer-sort losses, however, a maximum throughput of approximately 410,000 chips/week is realized for 300 mm wafers with 11/spl times/22 mm fields. Remarkably, the distribution of equipment states remains relatively unchanged across simulation experiments.
Starting Page	865
Ending Page	874
File Size	1686937
Page Count	10
File Format	PDF
ISBN	0780357809
DOI	10.1109/WSC.1999.823299
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1999-12-05
Access Restriction	Subscribed
Rights Holder	Winter Simulation Conf. Board of Dir.
Subject Keyword	X-ray lithography Synchrotrons Throughput Production Costs Semiconductor device modeling Frequency estimation Ultraviolet sources Systems engineering and theory Microelectronics
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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