NDLI: A CMOS fully integrated antenna array transmitter with on-chip skew and pulse-delay adjustment for millimeter-wave active imaging

Content Provider	IEEE Xplore Digital Library
Author	Nguyen Ngoc Mai Khanh Sasaki, M. Asada, K.
Copyright Year	2012
Description	Author affiliation: Graduate School of Engineering, and VDEC, The University of Tokyo, Japan (Asada, K.) \|\| VLSI Design and Education Center (VDEC), The University of Tokyo, Japan (Nguyen Ngoc Mai Khanh; Sasaki, M.)
Abstract	A fully-integrated 8-antenna array transmitter in 65-nm CMOS for short range and portable millimeter-wave (mm-wave) active imaging applications is presented. Each of 8 resistor-less pulse generators (PG) are connected to an on-chip dipole-patch antenna and to a 7-bit digitally programmable delay circuit (DPDC). A 20-bit on-chip jitter and relative skew measuring circuit is also implemented to dynamically calibrate pulse delays for the purpose of beamforming. On-chip skew measurement for eight antenna clocks is performed so that the DPDC's input codes align eight antennas' output pulses. Experimental results of on-chip relative pulse delay calibration and radiation patterns show that beamforming angles of the fully integrated antenna array can be calibrated by digital input codes and the on-chip skew adjustment circuit for active imaging applications.
Starting Page	163
Ending Page	166
File Size	690824
Page Count	4
File Format	PDF
ISBN	9781457713170
e-ISBN	9781457713187
DOI	10.1109/SiRF.2012.6160123
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-01-16
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Delay Antenna measurements Arrays Antenna arrays System-on-a-chip Clocks Imaging active imaging Integrated antenna CMOS pulse generator antenna array skew adjustment mm-wave
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
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9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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