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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Tri CaoHuu Winson Yong Kwangho Lee |
| Copyright Year | 1993 |
| Description | Author affiliation: Dept. of Electr. Eng., San Jose State Univ., CA, USA (Tri CaoHuu; Winson Yong; Kwangho Lee) |
| Abstract | There are many publications in the area of cache coherence for multiprocessor systems as shared memory has proved to be a very effective approach to high speed performance. However, most of the works reported are limited to applications of multiprocessor systems using a single protocol. As the complexity of the multiprocessor system increases, the demand for using mixed computers in one system is more and more pronounced. We present the design and implementation of universal read/write buffer which supports multiprocessor cache coherence of different protocols. An analysis of the approach is made, and the hardware and algorithm are discussed in detail. The complete design has been simulated successfully in VHDL. Our analysis shows that, for given system parameters, the performance of the cache system is improved by more than 200% if the universal buffer is used. |
| Starting Page | 785 |
| Ending Page | 790 |
| File Size | 597893 |
| Page Count | 6 |
| File Format | |
| ISBN | 0818641207 |
| ISSN | 10586393 |
| DOI | 10.1109/ACSSC.1993.342629 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 1993-11-01 |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Multiprocessing systems Protocols Application software Algorithm design and analysis Hardware Computational modeling Performance analysis |
| Content Type | Text |
| Resource Type | Article |
| Subject | Signal Processing Computer Networks and Communications |
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