NDLI: Low latency T-EMS decoder for non-binary LDPC codes

Content Provider	IEEE Xplore Digital Library
Author	Erbao Li Garcia-Herrero, F. Declercq, D. Gunnam, K. Lacruz, J.O. Valls, J.
Copyright Year	2013
Description	Author affiliation: Nvidia Corp., Santa Clara, CA, USA (Gunnam, K.) \|\| Inst. de Telecomun. y Aplic. Multimedia, Univ. Politec. de Valencia, Gandia, Spain (Garcia-Herrero, F.; Valls, J.) \|\| Electr. Eng. Dept., Univ. de Los Andes, Merida, Venezuela (Lacruz, J.O.) \|\| ETIS ENSEA, Univ. Cergy-Pontoise, Cergy-Pontoise, France (Erbao Li; Declercq, D.)
Abstract	Check node update processing for non-binary LDPC (NB-LDPC) architectures requires a large number of clock cycles, which limits the achievable throughput to tens of Mbps for high rate codes. In this work, we propose a new NB-LDPC architecture based on the Trellis-EMS (T-EMS) algorithm that reduces the number of clock cycles by a factor of $d_{c},$ by adding an extra column to the trellis. This feature makes our solution the fastest decoder published for NB-LDPC codes, compared to the recent state-of-the-art solutions. Our proposed architecture has been implemented for two different high-rate codes: a (N=3888, K=3456) NB-LDPC over GF(4) and a (N=837, K=726) NB-LDPC over GF(32). The first one achieves a throughput of 3.2 Gbps on a 40nm CMOS process and the second one reaches 484 Mbps on a 90nm CMOS technology.
Sponsorship	IEEE Signal Process. Soc.
Starting Page	831
Ending Page	835
File Size	353810
Page Count	5
File Format	PDF
e-ISBN	9781479923908
DOI	10.1109/ACSSC.2013.6810404
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-11-03
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Decoding Reliability Complexity theory Parity check codes Throughput Indexes Equations high-speed T-EMS NB-LDPC message passing decoder low latency hardware decoder architecture
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
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3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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