NDLI: Achieving flexibility in LDPC code design by absorbing set elimination

Content Provider	IEEE Xplore Digital Library
Author	Jiajun Zhang Jiadong Wang Srinivasa, S.G. Dolecek, L.
Copyright Year	2011
Description	Author affiliation: Western Digital Corporation, USA (Srinivasa, S.G.) \|\| Department of Electrical Engineering, University of California, Los Angeles, USA (Jiajun Zhang; Jiadong Wang; Dolecek, L.)
Abstract	Low-density parity-check (LDPC) codes are attractive since their performance is known to approach the Shannon limits for suitably large block lengths. However, for moderate block lengths, error floors still jeopardize the performance even of well-designed LDPC codes. Previous work has shown that the error floor of a broad class of LDPC codes is due to certain graphical structures called absorbing sets. Separable, circulant-based (SCB) codes represent a general family of high-performance, hardware-friendly LDPC codes built out of circulants. A recently proposed technique applies row selection and column elimination methods to SCB codes to dramatically decrease error floors by avoiding certain small dominant absorbing sets in a principled way. This paper focuses on improving the greedy column elimination method to achieve greater flexibility in code rate while provably avoiding small dominant absorbing sets. Flexibility and low implementation complexity are therefore possible without sacrificing SCB code performance.
Starting Page	669
Ending Page	673
File Size	174005
Page Count	5
File Format	PDF
ISBN	9781467303217
ISSN	10586393
e-ISBN	9781467303231
DOI	10.1109/ACSSC.2011.6190087
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-11-06
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Parity check codes Approximation algorithms Strontium Algorithm design and analysis Greedy algorithms Complexity theory Decoding
Content Type	Text
Resource Type	Article
Subject	Signal Processing Computer Networks and Communications

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Approximated sum-product decoding for LDPC codes

Low-complexity decoding of LDPC codes using reduced-set WBF-based algorithms

Approximated Box-Plus Decoding of LDPC Codes

A reduced-complexity successive-cancellation decoding algorithm for polar codes

A low-complexity rate-compatible LDPC decoder

Reduced-complexity decoding implementation of QC-LDPC codes with modified shuffling

A new simplified RRWBF decoding algorithm for LDPC decoder in CMMB

New decoding scheme for LDPC codes based on simple product code structure

A Simplified Min-Sum Decoding Algorithm for Non-Binary LDPC Codes

Achieving flexibility in LDPC code design by absorbing set elimination

Similar Documents

Approximated sum-product decoding for LDPC codes

Low-complexity decoding of LDPC codes using reduced-set WBF-based algorithms

Approximated Box-Plus Decoding of LDPC Codes

A reduced-complexity successive-cancellation decoding algorithm for polar codes

A low-complexity rate-compatible LDPC decoder

Reduced-complexity decoding implementation of QC-LDPC codes with modified shuffling

A new simplified RRWBF decoding algorithm for LDPC decoder in CMMB

New decoding scheme for LDPC codes based on simple product code structure

A Simplified Min-Sum Decoding Algorithm for Non-Binary LDPC Codes

Achieving flexibility in LDPC code design by absorbing set elimination