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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Tenca, A.F. Kyung-Nam Han Tran, D. |
| Copyright Year | 2007 |
| Description | Author affiliation: Synopsys, Inc., Hillsboro (Tenca, A.F.; Kyung-Nam Han; Tran, D.) |
| Abstract | Manipulation of denormalized numbers in circuits for floating-point operations comes at a reasonable cost. IEEE standard 754 defines the use of denormalized values. They are incorporated into high-performance CPUs and they are gaining space in commercial products. This paper describes the extra processing steps that are required for the manipulation of denormalized numbers in floating-point addition and floating-point multiplication. It also provides the results of several experiments that show the average additional cost that designers face when creating these basic operations using cell libraries, for some CMOS technologies. |
| Starting Page | 348 |
| Ending Page | 352 |
| File Size | 3675298 |
| Page Count | 5 |
| File Format | |
| ISBN | 9781424421091 |
| ISSN | 10586393 |
| DOI | 10.1109/ACSSC.2007.4487227 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2007-11-04 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Costs CMOS technology Hardware Libraries Circuit synthesis Digital arithmetic Floating-point arithmetic Integrated circuit technology Application software multiplication addition arithmetic denormalized numbers floating-point |
| Content Type | Text |
| Resource Type | Article |
| Subject | Signal Processing Computer Networks and Communications |
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