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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Guang Yang Harry Hsieh Xi Chen Balarin, F. Sangiovanni-Vincentelli, A. |
| Copyright Year | 2006 |
| Description | Author affiliation: Univ. of California, Berkeley, CA (Guang Yang) |
| Abstract | This paper focuses on quantitative constraints specified with logic of constraints (LOC) and coordination constraints with linear temporal logic (LTL) that are used in the specification, modeling, and validation of heterogeneous embedded system design. Quantity annotation is the principal approach for modeling performance information in Metropolis, our experiment platform. Quantitative constraints are then used to enforce and to refine simulation. They can also be used in synthesis settings especially for deciding system level parameters such as scheduling and hardware-software partitioning. Similarly, we utilize LTL in Metropolis to quickly refine the system behavior especially process coordinations. On the validation aspect, LOC and LTL are also used to specify assertions for simulation and for formal verification. We demonstrate our approach with a multimedia example from the industry. |
| Starting Page | 1469 |
| Ending Page | 1474 |
| File Size | 7666327 |
| Page Count | 6 |
| File Format | |
| ISBN | 1424407842 |
| ISSN | 10586393 |
| DOI | 10.1109/ACSSC.2006.355002 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2006-10-29 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Lab-on-a-chip Design methodology Formal verification Logic design Embedded system Analytical models Power system modeling Laboratories Job shop scheduling Refining |
| Content Type | Text |
| Resource Type | Article |
| Subject | Signal Processing Computer Networks and Communications |
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