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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Dick, C. Harris, F. |
| Copyright Year | 2003 |
| Description | Author affiliation: Signal Process. Group, Xilinx Inc., San Jose, CA, USA (Dick, C.) |
| Abstract | Orthogonal frequency division multiplexing (OFDM) based communication is increasingly being used in environments that exhibit severe multipath. While there are ASSP solutions for many common (e.g. 802.11a) and emerging standards, many communication systems, for example a military software radio, demand flexibility. The arithmetic requirements of an OFDM system can be very demanding. Even the ubiquitous 802.11a WLAN system has arithmetic requirements in the billions-of-operations per second region and cannot be satisfied even by high-end DSP microprocessors. This paper reports on the FPGA implementation of an OFDM transceiver. In addition to the FFT based modulator and demodulator, receiver synchronization and channel estimation is discussed. The FPGA resource requirements of the various sub-systems are reported and the design methodology employed for system design, verification and FPGA implementation is described. |
| Starting Page | 905 |
| Ending Page | 909 |
| File Size | 398787 |
| Page Count | 5 |
| File Format | |
| ISBN | 0780381041 |
| DOI | 10.1109/ACSSC.2003.1292045 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2003-11-09 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Field programmable gate arrays OFDM Physical layer Military standards Arithmetic Communication standards Software standards Military communication Software radio Wireless LAN |
| Content Type | Text |
| Resource Type | Article |
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