NDLI: Approach to the design of parity-checked arithmetic circuits

Content Provider	IEEE Xplore Digital Library
Author	Parhami, B.
Copyright Year	2002
Description	Author affiliation: Dept. of Electr. & Comput. Eng., California Univ., Santa Barbara, CA, USA (Parhami, B.)
Abstract	Achieving fault tolerance via parity checking is attractive due to low overhead in storage and interconnect. However, nonpreservation of parity during arithmetic operations makes it necessary to strip the parity bit before, and to restore it after, such operations. This either leaves the arithmetic part unprotected or else requires complex code conversions. We show that some redundant representations, which are often used for high performance anyway, support a way of designing low-overhead, fault-tolerant arithmetic hardware circuits. An added benefit is localized fault effects due to carry-free arithmetic. Our proposed fault tolerance strategy consists of a way of converting parity-encoded input values to even-parity redundant representations, performing arithmetic with redundant operands in such a way that parity is preserved, and, finally, converting any redundant result to standard parity-encoded output.
Starting Page	1084
Ending Page	1088
File Size	387463
Page Count	5
File Format	PDF
ISBN	0780375769
ISSN	10586393
DOI	10.1109/ACSSC.2002.1196951
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2002-11-03
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Arithmetic Fault tolerance Encoding Hardware Redundancy Strips Circuit faults Adders Computer errors Parity check codes
Content Type	Text
Resource Type	Article
Subject	Signal Processing Computer Networks and Communications

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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