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Content Provider | IEEE Xplore Digital Library |
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Author | Fahmy, H.A.H. Liddicoat, A.A. Flynn, M.J. |
Copyright Year | 2001 |
Description | Author affiliation: Comput. Syst. Lab., Stanford Univ., CA, USA (Fahmy, H.A.H.) |
Abstract | This work presents several techniques to improve the effectiveness of floating point arithmetic computations. A partially redundant number system is proposed as an internal format for arithmetic operations. The redundant number system enables carry free arithmetic operations to improve performance. Conversion from the proposed internal format back to the standard IEEE format is done only when an operand is written to memory. Efficient arithmetic units for floating point addition, multiplication and division are proposed using the redundant number system. This proposed system achieves overall better performance across all of the functional units when compared to state-of-the-art designs. The proposed internal format and arithmetic units comply with all the rounding modes of the IEEE 754 floating point standard. |
Starting Page | 875 |
Ending Page | 879 |
File Size | 490314 |
Page Count | 5 |
File Format | |
ISBN | 078037147X |
ISSN | 10586393 |
DOI | 10.1109/ACSSC.2001.987049 |
Language | English |
Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
Publisher Date | 2001-11-04 |
Publisher Place | USA |
Access Restriction | Subscribed |
Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
Subject Keyword | Floating-point arithmetic Laboratories USA Councils Signal processing Signal processing algorithms Circuits Sections ANSI standards Standards development Registers |
Content Type | Text |
Resource Type | Article |
Subject | Signal Processing Computer Networks and Communications |
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