NDLI: High-performance low-power polyphase channelizer chip-set

Content Provider	IEEE Xplore Digital Library
Author	Song, W.S. Vai, M.M. Nguyen, H.T. Horst, A.H.
Copyright Year	2000
Description	Author affiliation: Lincoln Lab., MIT, Lexington, MA, USA (Song, W.S.)
Abstract	A very-high-performance ultra-low-power signal processor chip-set has been developed for wideband adaptive radar and communications applications. The chip-set consists of a polyphase filter chip and a fast Fourier transform (FFT) chip. The chip-set performs polyphase channelization, which channelizes wideband digital data into multiple narrow subbands. The subsequent signal processing tasks such as adaptive beamforming, pulse compression, and space-time adaptive processing (STAP) are performed in the subband domain to mitigate dispersion effects. The power efficiency is achieved through highly optimized VLSI bit-level semi-systolic array technology. The chip-set was fabricated on a 0.25 micron bulk silicon CMOS process with the total two-chip die area of 1.6 square centimeters. The chip-set performs 54 billion arithmetic operations per second on 1.3 watts of power with 41 billion operations per second per watt power efficiency.
Starting Page	1691
Ending Page	1694
File Size	497888
Page Count	4
File Format	PDF
ISBN	0780365143
ISSN	10586393
DOI	10.1109/ACSSC.2000.911277
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2000-10-29
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Radar signal processing Array signal processing Signal processing Ultra wideband communication Ultra wideband radar Radar applications Filters Fast Fourier transforms Adaptive signal processing Pulse compression methods
Content Type	Text
Resource Type	Article
Subject	Signal Processing Computer Networks and Communications

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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