NDLI: A programmable interpolation and decimation structure for constant-rate high-speed /spl Sigma//spl Delta/-converters

Content Provider	IEEE Xplore Digital Library
Author	Magesacher, T. Gazsi, L.
Copyright Year	1999
Description	Author affiliation: Infineon Technol., Villach, Austria (Magesacher, T.)
Abstract	An area efficient programmable filter structure for sampling rate conversion by an arbitrary ratio for high speed constant-rate /spl Sigma//spl Delta/-converters is proposed. Utilizing cascaded lattice wave digital filters in a carry-save architecture with canonic signed-digit coefficients, oversampling ratio and filter characteristic can be programmed using minimum coefficient length. For the implemented 5/sup th/ order Bessel and 4/sup th/ order Butterworth filters used in a variable symbol rate digital subscriber line (DSL) system, the passband edge frequencies can be tuned from 20 kHz to 200 kHz in 2.6 kHz steps with only 25 bits per filter which cannot be achieved with any other IIR or FIR structure. Implementation results of the filters fabricated in a 0.35 /spl mu/m CMOS process using a standard static logic cell library are presented.
Starting Page	1410
Ending Page	1414
File Size	497895
Page Count	5
File Format	PDF
ISBN	0780357000
ISSN	10586393
DOI	10.1109/ACSSC.1999.831938
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1999-10-24
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Interpolation Finite impulse response filter Digital filters IIR filters DSL Sampling methods Lattices Passband Frequency CMOS process
Content Type	Text
Resource Type	Article
Subject	Signal Processing Computer Networks and Communications

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