NDLI: Repeater insertion to reduce delay and power in RC tree structures

Content Provider	IEEE Xplore Digital Library
Author	Adler, V. Friedman, E.G.
Copyright Year	1998
Description	Author affiliation: Dept. of Electr. Eng., Rochester Univ., NY, USA (Adler, V.)
Abstract	In large chips, the propagation delay of the data and clock signals is limited due to long resistive interconnect. The proper insertion of repeaters alleviates the quadratic increase in propagation delay with the interconnect length while decreasing the power dissipation by reducing the short-circuit current. These repeaters are inserted within different types of common resistive interconnect structures, such as a line or a tree. The application of repeaters to RC tree structures is discussed. A tree topology is a common interconnect structure frequently found in VLSI circuits. A short-channel transistor model is used as a foundation for the development of delay and power expressions to develop a design methodology for inserting repeaters into an RC tree network. Power dissipation expressions for these repeater structures are presented which consider both dynamic and short-circuit power. These design expressions are validated against simulated experiments with a maximum 11% and 16% deviation from SPICE for delay and power, respectively.
Starting Page	749
Ending Page	752
File Size	412935
Page Count	4
File Format	PDF
ISBN	0818683163
ISSN	10586393
DOI	10.1109/ACSSC.1997.680544
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1997-11-02
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Repeaters Tree data structures Integrated circuit interconnections Propagation delay Power dissipation Clocks Network topology Circuit topology Very large scale integration Design methodology
Content Type	Text
Resource Type	Article
Subject	Signal Processing Computer Networks and Communications

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