NDLI: Programming strategies to improve energy efficiency and reliability of ReRAM memory systems

Content Provider	IEEE Xplore Digital Library
Author	Manqing Mao Yu Cao Shimeng Yu Chakrabarti, C.
Copyright Year	2015
Description	Author affiliation: Sch. of Electr., Comput. & Energy Eng., Arizona State Univ., Tempe, AZ, USA (Manqing Mao; Yu Cao; Shimeng Yu; Chakrabarti, C.)
Abstract	Resistive RAM (ReRAM) has fast access time, ultra-low stand-by power and high reliability, making it a viable memory technology to replace DRAM for main memory. The 1-transistor-1-resistor (1T1R) ReRAM array has density comparable to that of a DRAM array and the advantages of lower programming energy and higher reliability compared to the ultra-high density ReRAM cross-point array. In this paper, we propose several novel write strategies for 1T1R ReRAM aiming at high performance, low power and high reliability. We reduce the write latency significantly compared to the baseline scheme by using the same WL voltages and improve energy consumption and endurance by choosing proper set line, bit line and word line settings. The SPICE simulation results demonstrate that appropriate choice of circuit operation parameters can help obtain 10× improvement in lifetime with 33.6% reduction in energy compared to the baseline. Also, among all proposed systems, configurations which consume higher write energy also have higher endurance. We evaluate the system-level parameters of a 1GB ReRAM memory using CACTI and GEM5. We show that all the proposed ReRAM systems can achieve a lifetime of 30 years by employing error control coding (ECC). Finally, we show that the ReRAM based main memory can outperform DRAM main memory with respect to IPC (5.5% higher) and energy consumption (39.4% lower) through proper choice of write scheme configurations.
Starting Page	1
Ending Page	6
File Size	3199152
Page Count	6
File Format	PDF
e-ISBN	9781467396042
DOI	10.1109/SiPS.2015.7344980
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2015-10-14
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Programming Reliability Random access memory Arrays Microprocessors Energy consumption main memory 1T1R ReRAM latency energy reliability IPC
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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