NDLI: Mapping visual signal processing onto multi-core platform via algorithm/architecture co-exploration

Content Provider	IEEE Xplore Digital Library
Author	Chun-Fu Chen Lee, G.G.C. Zheng-Han Yu Chun-Hsi Huang
Copyright Year	2014
Description	Author affiliation: Dept. of Electr. Eng., Nat. Cheng Kung Univ., Tainan, Taiwan (Chun-Fu Chen; Lee, G.G.C.; Zheng-Han Yu; Chun-Hsi Huang)
Abstract	Degree of parallelism and data communication should be investigated to achieve high performance for mapping algorithm onto multi-core platform since multi-core platform would concurrently process multiple tasks and lots of data would be transferred between storages and processors. This paper proposes a method to resolve the burden of increase on data transfer rate in parallel processing via the analysis on the dependency matrix of data flow graph. The proposed method does not bias any multi-core platform since it just considers the intrinsic characteristics of algorithm, i.e., data flow graph. This paper utilizes dependency matrix, which conveys the causality of data transfer, for quantifying data transfer rate and corresponding storage requirement; as a consequence, a feasible mapping result, which has smaller data transfer rate and acceptable storage requirement, was exploited. Furthermore, in conjunction with degree of parallelism quantification, this paper presents a comprehensive exploration on design space for mapping algorithm onto multi-core platform through dependency matrix. IBM Cell Broadband Engine is selected to be the targeted multi-core platform in this paper. Experimental results show that when six cores are used, our result can speedup 5.75x on average as compared to single-core case; in addition, by integrating the proposed method on data transfer analysis, about 46% cycles of data transfer could be saved and overall performance could be further increased to 7.51x on average in comparison with the scenario of single-core without data reuse.
Starting Page	1
Ending Page	6
File Size	392245
Page Count	6
File Format	PDF
ISBN	9781479965885
DOI	10.1109/SiPS.2014.6986094
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-10-20
Publisher Place	UK
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Data transfer Computer architecture Algorithm design and analysis Signal processing algorithms Program processors Parallel processing Space exploration IBM Cell Broadband Engine algorithm/architecture co-exploration degree of parallelism multi-core platform data transfer rate
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Mapping visual signal processing onto multi-core platform via algorithm/architecture co-exploration

Mapping Algorithms for Multiprocessor Tasks on Multi-Core Clusters

Cell BE BLAST Design Overview (2006)

Quantifying intrinsic parallelism via eigen-decomposition of dataflow graphs for algorithm/architecture co-exploration

Modeling Multi-Grain Parallelism on Heterogeneous Multi-core Processors: A Case Study of the Cell BE (2008)

Modeling Multi-Grain Parallelism on Heterogeneous Multi-core Processors: A Case Study of the Cell BE (2008)

Implementation of the nas lu benchmark on the ibm cell broadband engine.

Radar processing with the IBM Cell Broadband Engine

Parallel Modular Multiplication on Multi-core Processors

Mapping visual signal processing onto multi-core platform via algorithm/architecture co-exploration

Similar Documents

Mapping visual signal processing onto multi-core platform via algorithm/architecture co-exploration

Mapping Algorithms for Multiprocessor Tasks on Multi-Core Clusters

Cell BE BLAST Design Overview (2006)

Quantifying intrinsic parallelism via eigen-decomposition of dataflow graphs for algorithm/architecture co-exploration

Modeling Multi-Grain Parallelism on Heterogeneous Multi-core Processors: A Case Study of the Cell BE (2008)

Modeling Multi-Grain Parallelism on Heterogeneous Multi-core Processors: A Case Study of the Cell BE (2008)

Implementation of the nas lu benchmark on the ibm cell broadband engine.

Radar processing with the IBM Cell Broadband Engine

Parallel Modular Multiplication on Multi-core Processors

Mapping visual signal processing onto multi-core platform via algorithm/architecture co-exploration