NDLI: Algorithm and architecture of video segmentation hardware system with a programmable PE array

Content Provider	IEEE Xplore Digital Library
Author	Shao-Yi Chien Yu-Wen Huang Bing-Yu Hsieh Liang-Gee Chen
Copyright Year	2002
Description	Author affiliation: Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan (Shao-Yi Chien; Yu-Wen Huang; Bing-Yu Hsieh; Liang-Gee Chen)
Abstract	Video segmentation is a key unit in content-based video encoding systems, such as MPEG-4. Existing algorithms are too complex for real-time applications, and hardware implementation is infeasible because of the global and irregular operations. In this paper, a hardware system for video segmentation is proposed from algorithm level to hardware architecture level. A hardware-oriented algorithm is first proposed to generate accurate object masks with local pixel operations and morphological operations, which are suitable for hardware implementation. After that, the hardware architecture is designed based on partial-result-reuse architecture and programmable morphology PE array architecture, which can achieve both high flexibility and throughput. A prototype chip is implemented to achieve the processing speed of 30 QCIF frames per second and 7,680 morphological operations per second at 26 MHz. It also shows the hardware cost is small, and the proposed video segmentation hardware system is suitable to be integrated into any content-based video encoding systems.
Sponsorship	IEEE Signal Process. Soc. IEEE Circuits & Systems. Soc
Starting Page	21
Ending Page	26
File Size	535453
Page Count	6
File Format	PDF
ISBN	0780375874
ISSN	15206130
DOI	10.1109/SIPS.2002.1049679
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2002-10-16
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Hardware MPEG 4 Standard Change detection algorithms Encoding Image segmentation Morphological operations Morphology Throughput Real time systems Algorithm design and analysis
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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