NDLI: Performance trade-off for the Insulated Gate Bipolar Transistor: Buffer layer versus base lifetime reduction

Content Provider	IEEE Xplore Digital Library
Author	Hefner, Allen R. Blackburn, David L.
Copyright Year	1986
Description	Author affiliation: Semiconductor Electronics Division, National Bureau of Standards, Gaithersburg, MD 20899, United States (Blackburn, David L.) \|\| Electrical Engineering Department, University of Maryland, College Park, 20742, United States (Hefner, Allen R.)
Abstract	A one-dimensional analytic model for the Insulated Gate Bipolar Transistor (IGBT) which includes a high-doped buffer layer in the low-doped bipolar transistor base is developed. The model is used to perform a theoretical trade-off study between IGBTs with and without the buffer layer. The study is performed for devices of equal breakdown voltages, and the critical parameters chosen to “trade-off” are turn-off switching energy loss (related to turn-off time) and on-state voltage, both at a given current. In this study, as in reality, the two critical parameters are varied by: 1) adjusting the doping concentration and thickness of a buffer layer included as part of the bipolar transistor base, 2) adjusting the lifetime in the lowly doped bipolar transistor base with no buffer layer included, or by 3) a combination of 1) and 2). The results of the model predict that for equal breakdown voltages, an optimized device with a buffer layer has less switching energy loss for a given on-state voltage than an optimized device with no buffer layer.
Starting Page	27
Ending Page	38
File Size	1148265
Page Count	12
File Format	PDF
ISBN	9789996323270
ISSN	02759306
DOI	10.1109/PESC.1986.7415543
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1986-06-23
Publisher Place	Canada
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Charge carrier processes MOSFET Cathodes Epitaxial growth Substrates Insulated gate bipolar transistors Junctions
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

A Performance Trade-Off for the Insulated Gate Bipolar Transistor: Buffer Layer Versus Base Lifetime Reduction

An improved understanding for the transient operation of the power insulated gate bipolar transistor (IGBT)

The trench planar insulated gate bipolar transistor (TPIGBT)

Investigation and Improvement of high performance planar IGBT

Advanced carrier density enhancement technologies in insulated gate bipolar transistors

A new concept for a non punch through IGBT with MOSFET like switching characteristics

Optimization of 500V, P-channel VDMOS-LIGBT transistors

A novel double-gate Trench Insulated Gate Bipolar transistor with ultra-low on-state voltage

Novel Approach Toward Plasma Enhancement in Trench-Insulated Gate Bipolar Transistors

Performance trade-off for the Insulated Gate Bipolar Transistor: Buffer layer versus base lifetime reduction

Similar Documents

A Performance Trade-Off for the Insulated Gate Bipolar Transistor: Buffer Layer Versus Base Lifetime Reduction

An improved understanding for the transient operation of the power insulated gate bipolar transistor (IGBT)

The trench planar insulated gate bipolar transistor (TPIGBT)

Investigation and Improvement of high performance planar IGBT

Advanced carrier density enhancement technologies in insulated gate bipolar transistors

A new concept for a non punch through IGBT with MOSFET like switching characteristics

Optimization of 500V, P-channel VDMOS-LIGBT transistors

A novel double-gate Trench Insulated Gate Bipolar transistor with ultra-low on-state voltage

Novel Approach Toward Plasma Enhancement in Trench-Insulated Gate Bipolar Transistors

Performance trade-off for the Insulated Gate Bipolar Transistor: Buffer layer versus base lifetime reduction