NDLI: Implementation of Constrained Partitioned Broadband Antenna Array Processor Using the DFT Method

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Implementation of Constrained Partitioned Broadband Antenna Array Processor Using the DFT Method

Content Provider	IEEE Xplore Digital Library
Author	Jahromi, M.R.S. Godara, L.C.
Copyright Year	2006
Description	Author affiliation: Sch. of Inf. Technol. & Electr. Eng., New South Wales Univ., Canberra, ACT (Jahromi, M.R.S.; Godara, L.C.)
Abstract	Constrained partitioned processor is an alternative structure to an element space broadband antenna array processor using a tapped delay line filter with N taps. It consists of a fixed main beam to receive the signal from the look direction and a set of auxiliary beams for an L element array. The weighted sum of these beams is used to minimize the noise in the main beam requiring the inverse of a matrix of the order of LN times LN. This paper presents a method to estimate the weights of the auxiliary beams in parallel requiring the inverse of a matrix of the order of L times L and thus reducing the computational cost substantially. It is shown that the proposed method is more robust to look direction errors compared to the original structure
File Size	139241
File Format	PDF
ISBN	0780397363
DOI	10.1109/ICOSP.2006.344521
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2006-11-16
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Broadband antennas Antenna accessories Antenna arrays Signal processing Filters Australia Delay lines Array signal processing Information technology Educational institutions
Content Type	Text
Resource Type	Article

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