NDLI: A new non-volatile memory cell based on the flash architecture for embedded low energy applications: ATW (Asymmetrical Tunnel Window)

Content Provider	IEEE Xplore Digital Library
Author	Bartoli, J. Della Marca, V. Delalleau, J. Regnier, A. Niel, S. La Rosa, F. Postel-Pellerin, J. Lalande, F.
Copyright Year	2014
Description	Author affiliation: ST-Microelectron., Rousset, France (Bartoli, J.; Delalleau, J.; Regnier, A.; Niel, S.; La Rosa, F.) \|\| IM2NP, Aix-Marseille Univ., Marseille, France (Della Marca, V.; Postel-Pellerin, J.; Lalande, F.)
Abstract	In this paper we propose a new non-volatile charge trap memory architecture implemented on 200mm wafer in 90nm technology node. The aim of this work is to investigate an alternative and scalable solution for embedded low energy applications. The Asymmetrical Tunnel Window (ATW) memory cell has been developed in order to improve the programming operation during a hot carrier injection. The main property of this device is the presence of an asymmetrical tunnel oxide thickness along the channel. This characteristics enables an improvement in terms of current consumption and injection efficiency with respect to the standard Flash floating gate memory cell. In this work we describe the fabrication process of ATW memory cell and, using a commercial TCAD simulator and experimental results, we demonstrate the good functioning of our device thanks to the increased control gate/floating gate (CG/FG) coupling factor. To conclude we confirm the reliability performances with the endurance experiments up to 100k cycles.
Starting Page	117
Ending Page	120
File Size	499496
Page Count	4
File Format	PDF
ISBN	9781479939169
ISSN	1545827X
e-ISBN	9781479939176
DOI	10.1109/SMICND.2014.6966409
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-10-13
Publisher Place	Romania
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Computer architecture Microprocessors Nonvolatile memory Programming Logic gates Couplings Standards TCAD simulation non-volatile memory asymmetrical oxide thicknesses low energy endurance
Content Type	Text
Resource Type	Article

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