NDLI: A high speed modified Hopfield neural network and a design of character recognition system

Content Provider	IEEE Xplore Digital Library
Author	Chen, L.-C. Fan, J.-Y. Chen, Y.-S.
Copyright Year	1991
Description	Author affiliation: Inst. of Electron. Eng., Chung-Yung Christian Univ., Chung Li, Taiwan (Chen, L.-C.; Fan, J.-Y.; Chen, Y.-S.)
Abstract	A digital methodology called single error correction-single error detection (SECSED) is used to improve the learning and recall rules of the conventional Hopfield neural network. The XOR operator is used to implement the learning phase and the recall phase of the modified network. The bulk data processing of the modified Hopfield network is much faster than that of the conventional Hopfield network, because the improved method uses only XOR operations to avoid the carry-propagation of the multiplication and addition which is necessary in the learning and recall phases in the conventional Hopfield network. Because only the XOR operation is involved, it is very suitable for VLSI implementation of the neural network. Simulated results indicate that the modified Hopfield neural network can recognize each 24% noise-interfered pattern within 1 to 6 iterations with a recognition rate above 90%, while the conventional Hopfield neural network recognizes each small noise-interfered pattern with 6 to 12 iterations and a recognition rate below 5%.
Starting Page	308
Ending Page	314
File Size	439292
Page Count	7
File Format	PDF
ISBN	078030120X
DOI	10.1109/CCST.1991.202230
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1991-10-01
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Hopfield neural networks Character recognition Neural networks Pattern recognition Data processing Design engineering Speech processing Humans Phase detection Virtual colonoscopy
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
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9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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