NDLI: Safe operating area of power DMOS FETs

Content Provider	IEEE Xplore Digital Library
Author	Yilmaz, H. Tsui, T. Bencuya, I. Fortier, T. Owyang, K.
Copyright Year	1989
Description	Author affiliation: Siliconix Inc., Santa Clara, CA, USA (Yilmaz, H.; Tsui, T.; Bencuya, I.; Fortier, T.; Owyang, K.)
Abstract	The physical origin of the safe-operating-area (SOA) limitation in power DMOSFETs lies in the parasitic bipolar junction transistor (BJT) which is inherent to these devices. Direct-current SOA depends on transconductance and thermal variations of the drain-to-source current, while short-circuit SOA is strongly dependent on transconductance and the transient thermal impedance of the packaged device. It is shown that the power DMOSFET is inherently thermally stable. However, for operation at high voltages and low currents (DC-SOA), the built-in parasitic BJT could turn on locally due to solder voids, local high thermal impedance, and/or BJT cells with higher gain. Turn-on of the built-in BJT will cause device failure, limiting DC-SOA. DC-SOA can be improved with a lower temperature coefficient for drain current, which implies lower transconductance and thus improves SC-SOA due to lower power dissipation.
Starting Page	170
Ending Page	175
File Size	358590
Page Count	6
File Format	PDF
DOI	10.1109/PESC.1989.48487
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1989-06-26
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	FETs Semiconductor optical amplifiers MOSFET circuits Power MOSFET Temperature Electronic packaging thermal management Threshold voltage Transconductance Switching circuits Equations
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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