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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Tse, K.K. Chung, H. Hui, S.Y.R. |
| Copyright Year | 1998 |
| Description | Author affiliation: Dept. of Electron. Eng., City Univ. of Hong Kong, Kowloon, Hong Kong (Tse, K.K.) |
| Abstract | This paper presents a quadratic state-space modeling technique for analysis and simulation of power electronic converters. The methodology is based on using least-square-error fitting to derive a quadratic state-space representation for each topology, together with automatic determinations of switching topology. The algorithm integrates the advantages of calculating circuit responses at circuit level and determining switching instants at device level. Several key features of the new model that leads to significant improvements in computational efficiency include: (1) its simplicity of using quadratic polynomial representation for each circuit topology; (2) its directness of calculating the switching instants; and (3) its generality of determining valid topology without prior understanding of the switching relationships. Several examples illustrating the generality and simulation speed of the proposed approach are presented. The accuracy of the new approach is verified with the exact method. The computational efficiency is demonstrated by comparing its simulation time with the commercial software using a stepwise integration algorithm. |
| Starting Page | 1069 |
| Ending Page | 1075 |
| File Size | 584136 |
| Page Count | 7 |
| File Format | |
| ISBN | 0780344898 |
| ISSN | 02759306 |
| DOI | 10.1109/PESC.1998.703137 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 1998-05-22 |
| Publisher Place | Japan |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Analytical models Circuit topology Circuit simulation Power electronics Switching circuits Computational modeling Switches Switching converters Computational efficiency Network topology |
| Content Type | Text |
| Resource Type | Article |
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