NDLI: A systolic architecture for computation of the manipulator inertia matrix

Content Provider	IEEE Xplore Digital Library
Author	Amin-Javaheri, M. Orin, D.
Copyright Year	1987
Description	Author affiliation: Ohio State University, Columbus, OH, USA (Amin-Javaheri, M.)
Abstract	Systolic architectures consisting of 1, N, and N(N + 1)/2 processors are presented for computing the inertia matrix. A VLSI-based Robotics Processor which is under development is the fundamental component of the architecture. Its major elements are a 32-bit floating-point multiplier, 32- bit floating-point adder, triple-port memory, and four I/O ports for external communication which are interconnected to facilitate implementation of robotics operations. The algorithm used is based on recursive computation of the inertial parameters of sets of composite rigid bodies and is programmed to exploit any inherent parallelism. Good results are obtained for the N-processor and N(N + 1)/2- processor configurations which give a compute time delay which is of O(N). In addition, I/O time and idle time due to processor synchronization as well as CPU utilization and on-chip memory size are fully included in the evaluation and indicate the feasibility and effectiveness of the design.
Starting Page	647
Ending Page	653
File Size	665597
Page Count	7
File Format	PDF
DOI	10.1109/ROBOT.1987.1087925
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1987-03-01
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Computer architecture Manipulator dynamics Robots Jacobian matrices Concurrent computing Parallel processing Delay effects Equations Orbital robotics Ear
Content Type	Text
Resource Type	Article

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