NDLI: Integrated power clock generators for low energy logic

Content Provider	IEEE Xplore Digital Library
Author	Maksimovic, D. Oklobdzija, V.G.
Copyright Year	1995
Description	Author affiliation: Dept. of Electr. & Comput. Eng., Colorado Univ., Boulder, CO, USA (Maksimovic, D.)
Abstract	Low-energy (adiabatic) logic families have been proposed to reduce energy consumption of VLSI logic devices. Instead of the conventional DC power supply, these logic families require AC power supplies (power clocks) that allow energy recovery and also serve as timing clocks for the logic. In this paper, high-frequency resonant DC/AC inverters are proposed as power clock generators where all power switches and control circuitry are integrated on the same chip with low-energy logic. This results in better system efficiency and simpler power distribution. Closed-form results are derived to facilitate efficiency-optimized design of the proposed power clock generators. To illustrate system integration and energy savings, the optimized power clock is used to supply a novel clocked CMOS adiabatic logic (CAL).
Starting Page	61
Ending Page	67
File Size	635315
Page Count	7
File Format	PDF
ISBN	0780327306
DOI	10.1109/PESC.1995.474793
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1995-06-18
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Clocks Power generation Logic devices Power supplies CMOS logic circuits Energy consumption Very large scale integration Timing Resonance Inverters
Content Type	Text
Resource Type	Article

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