NDLI: A digital neural network VLSI with on-chip learning using stochastic pulse encoding

Content Provider	IEEE Xplore Digital Library
Author	Oteki, S. Hashimoto, A. Furuta, T. Motomura, S. Watanabe, T. Stork, D.G. Eguchi, H.
Copyright Year	1993
Description	Author affiliation: LSI Res. & Dev. Center, Ricoh Co. Ltd., Osaka, Japan (Oteki, S.; Hashimoto, A.)
Abstract	A digital neural network VLSI chip, RN200 has been developed and fabricated. Sixteen neurons and totally 256 synapses are integrated in a 13.73/spl times/13.73 mm/sup 2/ VLSI chip, fabricated by RICOH 0.8 /spl mu/m CMOS technology. Multiple-layer neural network can be made by combining two or more-chips. Signals within the network (e.g., activations, error signals, connection weights) are represented by stochastic digital pulse trains. Both feed forward and learning processes are efficiently implemented with simple logical gates. Our novel approach for approximating the derivative of activation function is described. The approximation circuit requires only a few gates. Multiple-RNG architecture is adopted to ensure the random distribution of pulses. Both seeds and configurations of the random number generators on the chip can be updated dynamically and randomly by this mechanism. The effectiveness of the derivative and the Multiple-RNG architecture are simulated and verified with the learning performance in a hand-written character recognition problem. The chip can perform 5.12 gigapulse operations per second. It corresponds to effective neural computing rate of 40M CPS or 40M CUPS.
Starting Page	3039
Ending Page	3045
File Size	605077
Page Count	7
File Format	PDF
ISBN	0780314212
DOI	10.1109/IJCNN.1993.714361
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1993-10-25
Publisher Place	Japan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Neural networks Very large scale integration Network-on-a-chip Stochastic processes Encoding CMOS technology Neurons Feeds Circuits Random number generation
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
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3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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