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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Stokes, D. May, G. Chen, V. Lin, Y.T. |
| Copyright Year | 1997 |
| Description | Author affiliation: Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA (Stokes, D.) |
| Abstract | As geometries in integrated circuits continue to decrease, the elimination of submicron defects caused by particles generated within semiconductor processes becomes more and more critical. These particles can cause surface defects which lead to reduced yield. While 100% inspection of processed wafers during fabrication provides the most accurate means for detecting these anomalies, it is also very time-consuming and costly. This cost can be mitigated through the use of automated in-situ particle monitoring systems (ISPMs) which provided real-time estimates of particle counts in process chambers for different categories of particle sizes. However, the challenge is to correlate ISPM measurements with actual surface defects. In this paper, neural network models are used to estimate the number of particles that are deposited on a semiconductor wafer based on ISPM data collected during processing in a reactive ion etching (RIE) chamber. This particle prediction methodology can lead to reduced resting costs and more accurate defect detection. |
| Starting Page | 169 |
| Ending Page | 173 |
| File Size | 421739 |
| Page Count | 5 |
| File Format | |
| ISBN | 0780341228 |
| DOI | 10.1109/ICNN.1997.611658 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 1997-06-12 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Etching Neural networks Costs Geometry Integrated circuit yield Inspection Fabrication Computerized monitoring Real time systems Semiconductor device modeling |
| Content Type | Text |
| Resource Type | Article |
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