NDLI: Hardware neural network implementation of tracking system

Content Provider	IEEE Xplore Digital Library
Author	Lendaris, G.G. Pap, R.M. Saeks, R.E. Thomas, C.R. Akita, R.M.
Copyright Year	1994
Description	Author affiliation: Accurate Autom. Corp., Chattanooga, TN, USA (Lendaris, G.G.; Pap, R.M.; Saeks, R.E.; Thomas, C.R.)
Abstract	A neural network (NN) filter/target-tracking system has been developed as reported in Pap et al. (1992). The design accepts and inputs signal data to a noise/target classifier which uses spectral estimation techniques to distinguish noise from real targets. In that design, the NN is used to calculate the coefficients of an auto regressive linear predictive filter. The current evolution of that design invokes the use of Lagrange multiplier methods to incorporate known characteristics of the noise vs. signal. A (linear) Hopfield NN is used to perform the constrained optimization to solve for the filter coefficients. This algorithm has been demonstrated on real stochastic data. The filter resulting from this process succeeds in reducing the noise, whose structure was learned by the NN. Not only did this approach reduce structured noise without target attenuation or the addition of a 'ghost' signal, but it also lowered the base level of the resultant signal significantly. The overall concept has been tested and validated using real data on a workstation and the hardware NN implementation has been validated. This concept has been tested on the AAC Multiple Instruction Multiple Data (MIMD) Neural Network Processor (NNP) hardware. Each processor runs at 140 million connections/sec with 8 K neurons. An expanded version of the system performs a total of a billion plus connections/sec. Unlike classical SIMD NN architectures, which are really general purpose array processors, this MIMD system architecture was custom designed for NN applications.
Starting Page	451
Ending Page	460
File Size	460874
Page Count	10
File Format	PDF
ISBN	0780320263
DOI	10.1109/NNSP.1994.366025
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1994-09-06
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Neural network hardware Neural networks Nonlinear filters Noise reduction Noise level Signal processing Testing Target tracking Signal design Lagrangian functions
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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