NDLI: Improved Architectures for Range Encoding in Packet Classification System

Content Provider	IEEE Xplore Digital Library
Author	Xin He Peddersen, J. Parameswaran, S.
Copyright Year	2010
Abstract	Packet classification is an important aspect of modern network systems. Packet classification systems have traditionally been built utilizing Ternary Content Addressable Memory (TCAM) due to the high throughput needed. However, TCAMs are expensive in terms of area and power consumption. An alternative to TCAM based systems using SRAM and a novel rule encoding method has been proposed to match multiple packets simultaneously (using multiple store_compare_units). This alternative achieves similar or better throughput than the traditional TCAM approach while occupying smaller space and consuming less energy. This paper revamps the existing SRAM-based architecture to reduce area and power consumption without threatening throughput. Two methods are shown. The first method allows for range encoding SRAMs to be shared between store_compare_units (SCUs) to lower area and power consumption with minor effect on throughput. The second method discusses a hybrid system allowing rules with prefixes (single rules) and ranges (rules which match a range of addresses, usually translated to many prefixes) to exist in parallel for the same domain. This allows for lower power consumption than utilizing fixed range encoding due to optimization of the ruleset. Results show that this hybrid architecture saves more than 20% of power/field if half of the TCP ports contain ranges (and the other half contains prefixes). The new extensions have been tested in over ten benchmarks (including the SNORT ruleset) to verify the claimed improvements.
Starting Page	10
Ending Page	19
File Size	503676
Page Count	10
File Format	PDF
ISBN	9781424476282
e-ISBN	9781424476275
DOI	10.1109/NCA.2010.9
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-07-15
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Encoding Throughput Power demand Memory management Clocks Australia Random access memory LOP Packet Classification Range Encoding
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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