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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Vacca, M. Frache, S. Graziano, M. Zamboni, M. |
| Copyright Year | 2012 |
| Description | Author affiliation: Dipartimento di Elettronica e Telecomunicazioni, Politecnico di Torino, Italy (Vacca, M.; Frache, S.; Graziano, M.; Zamboni, M.) |
| Abstract | Many new emerging technologies are currently studied as possible substitute of CMOS transistors. Among these technologies one of the most interesting is the NanoMagnetic Logic (NML), which combines computation and memory in the same device. Although many works analyze this technology at the device level, an high level analysis on complex circuits is required to fully understand its potentialities. As an absolute novelty we present in this work a tool for automatic synthesis and simulation of NML circuits. Starting from a circuit described using VHDL language, the circuit physical layout is extracted, using all the technological constraints actually known. The circuit is then simulated using a behavioral model of the basic logic gates. This model is validated through micromagnetic low level simulations. Using ToPoliNano, which is highly modular and customizable, the possibility to explore and analyze realistic and complex NML circuits will be greatly improved. |
| Starting Page | 1 |
| Ending Page | 6 |
| File Size | 2328392 |
| Page Count | 6 |
| File Format | |
| ISBN | 9781467321983 |
| ISSN | 19449399 |
| e-ISBN | 9781467322003 |
| DOI | 10.1109/NANO.2012.6321982 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2012-08-20 |
| Publisher Place | United Kingdom |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Clocks Logic gates Silicon |
| Content Type | Text |
| Resource Type | Article |
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