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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Soo Jin Park Byoung Hee Yoon Kwang Sub Yoon Heung Soo Kim |
| Copyright Year | 2004 |
| Description | Author affiliation: Dept. of Electron. Eng., Inha Univ., Inchon, South Korea (Soo Jin Park; Byoung Hee Yoon; Kwang Sub Yoon; Heung Soo Kim) |
| Abstract | A multi-valued logic (MVL) pass gate is an important element in configuring multi-valued logic. Multiple logical levels, which are different from binary pass gates, are required to be discriminated in MVL pass gates. In this paper, we designed the quaternary MIN (QMIN)/negated MIN (QNMIN) gate, and the quaternary MAX (QMAX)/negated MAX (QNMAX) gate using double pass-transistor logic (DPL) with neuron MOS (vMOS) threshold gates. In addition, we designed quaternary truncated sum (QTS) and quaternary truncated difference (QTD) gates using vMOS down literal circuits (DLC). The DPL improved the gate speed without increasing the input capacitance. It has a symmetrical arrangement and double-transmission characteristics. The threshold gates are composed of vMOS DLC. The proposed gates obtain the signal value, to realize various multi threshold voltage circuits. In this paper, these circuits use a 3 V power supply voltage and the parameters of the 0.35 /spl mu/m N-well 2-poly 4-metal CMOS technology. HSPICE simulation results are also presented. |
| Sponsorship | IEEE Comput. Soc. Tech. Committee on Multiple-Valued Logic Univ. Toronto Altera Corp |
| Starting Page | 198 |
| Ending Page | 203 |
| File Size | 360427 |
| Page Count | 6 |
| File Format | |
| ISBN | 0769521304 |
| ISSN | 0195623X |
| DOI | 10.1109/ISMVL.2004.1319941 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2004-05-22 |
| Publisher Place | Canada |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Logic design Logic circuits Logic gates Neurons Multivalued logic Page description languages CMOS technology Capacitance Threshold voltage Power supplies |
| Content Type | Text |
| Resource Type | Article |
| Subject | Mathematics Computer Science |
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