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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Onneweer, S. Kerkhoff, H. Butler, J. |
| Copyright Year | 1988 |
| Description | Author affiliation: Twente Univ., Enschede, Netherlands (Onneweer, S.; Kerkhoff, H.) |
| Abstract | A set of CAD (computer-aided design) tools for the synthesis and layout generation of multiple-valued current-mode CMOS logic (CMCL) circuits is described. The synthesis method is based on the cost-table method. The general circuit structure, the cost-table functions, and the decomposition procedure used in the synthesis program are explained. The program is based on a logically complete set of basic elements for CMCL circuits. After circuit synthesis, the actual layout is generated using standard-cell IC design tools. |
| Starting Page | 21 |
| Ending Page | 30 |
| File Size | 700216 |
| Page Count | 10 |
| File Format | |
| ISBN | 0818608595 |
| DOI | 10.1109/ISMVL.1988.5144 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 1988-01-01 |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Design automation CMOS logic circuits Circuit synthesis Mirrors Logic circuits Cost function Logic design CMOS integrated circuits Very large scale integration Design methodology |
| Content Type | Text |
| Resource Type | Article |
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