NDLI: Design and implementation of error detection and correction circuitry for multilevel memory protection

Content Provider	IEEE Xplore Digital Library
Author	Polianskikh, B. Zilic, Z.
Copyright Year	2002
Description	Author affiliation: Dept. of Electr. & Comput. Eng., McGill Univ., Montreal, Que., Canada (Polianskikh, B.; Zilic, Z.)
Abstract	Traditional memories use only two levels per cell (0/1), which limits their storage capacity to 1 bit per cell. By doubling the cell capacity, we increase the density of the memory at the expense of its reliability. There are several types of memories that employ multi-level techniques. The subject of this paper is the design of a multi-level dynamic random access memory (MLDRAM). The problem of its reliability is investigated and a practical solution is proposed. The solution is based on the organization of the error-correcting code (ECC) that is tuned to the MLDRAM implementation. Conventional memories employ single-error-correcting and double-error-detecting (SEC-DED) ECCs. While such codes have been considered for MLDRAMs, their use is inefficient, due to likely double-bit errors in a single cell. For this reason, we propose an induced ECC architecture that uses ECC in such a way that no common error corrupts two bits. Induced ECC allows a significant increase in the reliability of the MLDRAM, by making use of improved check-bit generation circuitry that allows us to use less space for the parity-bit generation circuitry. The suggested approach is able to correct a two-bit error in a two-bits-per-cell MLDRAM, which the basic ECC cannot correct. The proposed solutions make the MLDRAM more tolerant to any kind of fault, and consequently more practical for mass production.
Sponsorship	IEEE Comput. Soc Tech. Committee on Multiple-Valued Logic Univ. Massachusetts, Boston
Starting Page	89
Ending Page	95
File Size	322616
Page Count	7
File Format	PDF
ISBN	0769514626
DOI	10.1109/ISMVL.2002.1011075
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2002-05-15
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Error correction Protection Error correction codes Voltage Mass production System-on-a-chip Computer errors DRAM chips Circuit faults Hardware
Content Type	Text
Resource Type	Article

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