NDLI: Power efficient inter-module communication for digit-serial DSP architectures in deep-submicron technology

Content Provider	IEEE Xplore Digital Library
Author	Dhaou, I.B. Dubrova, E. Tenhunen, H.
Copyright Year	2001
Description	Author affiliation: Electron. Syst. Design Lab., R. Inst. of Technol., Stockholm, Sweden (Dhaou, I.B.)
Abstract	This paper investigates the use of quaternary current mode signaling to minimize the power dissipation associated with inter-module communication. We formulate a condition specifying when the insertion of the encode-decoder pair between the two modules results in a reduction of the overall power consumption of the system. An algorithm LIBCOM is developed which utilizes this condition to insert the encoder-decoder pair between the two modules only if it is advantageous. The HSPICE results obtained for 0.35 /spl mu/m CMOS process show that LIBCOM can reduce the power consumption by 15%. As technology scales down, the power saved by our algorithm can be several orders of magnitude higher.
Sponsorship	IEEE Comput. Soc. Tech. Committee on Multiple-Valued Logic
Starting Page	61
Ending Page	66
File Size	483414
Page Count	6
File Format	PDF
ISBN	0769510833
ISSN	0195623X
DOI	10.1109/ISMVL.2001.924555
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2001-05-22
Publisher Place	Poland
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Digital signal processing Decoding Energy consumption CMOS technology Integrated circuit interconnections Delay Circuit faults Capacitance Costs Power system interconnection
Content Type	Text
Resource Type	Article
Subject	Mathematics Computer Science

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