NDLI: The output permutation for the multiple-valued logic minimization with universal literals

Content Provider	IEEE Xplore Digital Library
Author	Hozumi, T. Kakusho, O. Hata, Y.
Copyright Year	1999
Description	Author affiliation: Dept. of Econ. & Inf. Sci., Hyogo Univ., Japan (Hozumi, T.)
Abstract	This paper shows the effectiveness of an output permutation for the implementation of current-mode CMOS circuits. A combination of a simple function and an output permutation can realize a difficult function and cost for the combination will be lower than the cost for a difficult function. The output permutation can be realized by a universal literal and we can calculate the cost. We first examine the all combinations of universal literals and output permutations and show that some combinations can realize one-variable functions with lower costs. Next, we minimize two-variable functions and compare the costs with the costs obtained by some output permutations. As a result, we show that about 70% functions can reduce the costs and their reduction ratio is about 12% on average.
Starting Page	105
Ending Page	109
File Size	38754
Page Count	5
File Format	PDF
ISBN	0769501613
ISSN	0195623X
DOI	10.1109/ISMVL.1999.779703
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1999-05-20
Publisher Place	Germany
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Cost function CMOS logic circuits Logic functions Minimization methods Information science CMOS technology Circuit synthesis Simulated annealing
Content Type	Text
Resource Type	Article
Subject	Mathematics Computer Science

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