NDLI: Multiple-valued floating-gate-MOS pass logic and its application to logic-in-memory VLSI

Content Provider	IEEE Xplore Digital Library
Author	Hanyu, T. Teranihi, K. Kameyama, M.
Copyright Year	1998
Description	Author affiliation: Dept. of Comput. & Math. Sci., Tohoku Univ., Sendai, Japan (Hanyu, T.)
Abstract	A new logic-in-memory VLSI architecture based on multiple-valued floating-gate MOS pass logic is proposed to solve communication bottleneck between memory and logic modules. Multiple-valued stored data are represented by the threshold voltage of a floating-gate MOS transistor, so that a single floating-gate MOS transistor is effectively employed to merge multiple-valued threshold-literal and pass-switch functions. Since, multiple-valued pass-transistor network is realized by multiple-valued threshold-literal and pass-switch functions, it can be designed compactly by using floating-gate MOS transistors. As an example of typical logic-in memory VLSI systems, a fully parallel magnitude comparator is also presented. The performance of the proposed multiple-valued logic-in-memory VLSI is about 26 times higher than that of the corresponding implementation based on a binary content-addressable memory under a 0.8 /spl mu/m flash EEPROM technology. Moreover, its effective chip area and power dissipation are reduced to about 42 and 20 percents, respectively, in comparison with those of binary implementation.
Starting Page	270
Ending Page	275
File Size	165565
Page Count	6
File Format	PDF
ISBN	0818683716
ISSN	0195623X
DOI	10.1109/ISMVL.1998.679469
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1998-05-29
Publisher Place	Japan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Logic Very large scale integration
Content Type	Text
Resource Type	Article
Subject	Mathematics Computer Science

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