NDLI: Energy and area efficient hardware implementation of 4K Main-10 HEVC decoder in Ultra-HD Blu-ray player and TV systems

Content Provider	IEEE Xplore Digital Library
Author	Tsu-Ming Liu Yung-Chang Chang Chih-Ming Wang Hue-Min Lin Chia-Yun Cheng Chun-Chia Chen Min-Hao Chiu Sheng-Jen Wang Ping Chao Meng-Jye Hu Fu-Chun Yeh Shun-Hsiang Chuang Hsiu-Yi Lin Ming-Long Wu Che-Hong Chen Chia-Lin Ho Chi-Cheng Ju
Copyright Year	2015
Description	Author affiliation: Mediatek Inc., Hsinchu, Taiwan (Tsu-Ming Liu; Yung-Chang Chang; Chih-Ming Wang; Hue-Min Lin; Chia-Yun Cheng; Chun-Chia Chen; Min-Hao Chiu; Sheng-Jen Wang; Ping Chao; Meng-Jye Hu; Fu-Chun Yeh; Shun-Hsiang Chuang; Hsiu-Yi Lin; Ming-Long Wu; Che-Hong Chen; Chia-Lin Ho; Chi-Cheng Ju)
Abstract	A 4K and Main-10 HEVC video decoder LSI is fabricated in a 28nm CMOS process. It adopts a block-concealed processor (BcP) to improve the visual quality and a bandwidth-suppressed processor (BsP) is newly designed to reduce 30% and 45% of external data accesses in playback and gaming scenario, respectively. It features fully core scalable (FCS) architecture which lowers the required working frequency by 65%. A 10-bit compact scheme is proposed to reduce the frame buffer space by 37.5%. Moreover, a multi-standard architecture reduces are by 28%. It achieves 530Mpixels/s throughput which is two times larger than the state-of-the-art HEVC design [2] and consumes 0.2nJ/pixel energy efficiency, enabling real-time 4K video playback in Ultra-HD Blu-ray player and TV systems.
Starting Page	1
Ending Page	6
File Size	1479369
Page Count	6
File Format	PDF
ISBN	9781479970827
DOI	10.1109/ICME.2015.7177399
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2015-06-29
Publisher Place	Italy
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Decoding Streaming media Standards Random access memory TV Computer architecture Power capacitors H.265 ultra-HD HEVC
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in