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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Yen-Kuang Chen Holliman, M. Debes, E. |
| Copyright Year | 2002 |
| Description | Author affiliation: Intel Labs., Santa Clara, CA, USA (Yen-Kuang Chen; Holliman, M.; Debes, E.) |
| Abstract | This paper characterizes selected workloads of multimedia applications on current superscalar architectures, and then it characterizes the same workloads on Intel hyper-threading technology. This technology enables multiple threads to run in parallel on a processor, by interleaving instructions from different threads in the pipeline. The workloads, including video encoding, decoding, and watermark detection, are optimized for the Intel Pentium 4 processor. Even if the workloads are very well optimized for the Pentium 4 processor, most of the modules in these well-optimized workloads cannot fully utilize all the execution units available in the microprocessor, due to the inherently sequential constitution of the algorithms. Some of the modules are memory-bounded, while some are computation-bounded. Therefore, hyper-threading technology is a promising architecture feature that allows more CPU resources to be used at a given moment. Our goal is to provide a better explanation of the performance improvements that are possible in multimedia applications using hyper-threading technology. We demonstrate different task partition/scheduling schemes and discuss their trade-offs so that the reader can understand how to develop efficient applications on processors with hyper-threading technology. |
| Starting Page | 193 |
| Ending Page | 196 |
| File Size | 399897 |
| Page Count | 4 |
| File Format | |
| ISBN | 0780373049 |
| DOI | 10.1109/ICME.2002.1035546 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2002-08-26 |
| Publisher Place | Switzerland |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Yarn Interleaved codes Pipelines Encoding Decoding Watermarking Microprocessors Constitution Computer architecture Processor scheduling |
| Content Type | Text |
| Resource Type | Article |
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