NDLI: Hardware accelerated Wavelet Transform and de-noising for pattern recognition

Content Provider	IEEE Xplore Digital Library
Author	Javaid, S. Zaidi, S.S.H.
Copyright Year	2014
Description	Author affiliation: Dept. of Electron. & Power Eng., Nat. Univ. of Sci. & Technol., Islamabad, Pakistan (Javaid, S.; Zaidi, S.S.H.)
Abstract	Wavelet Transform is a widely used tool in signal processing which helps in localizing a signal in both time and frequency domain. This is in contrast to FFT which can only resolve a signal in frequency domain. Additionally, Wavelet Transform has been widely employed by electrical machines researchers for fault diagnosis and prognosis especially as means to extract features for classification purposes. The problem though with both machine learning algorithms and Wavelet Transform is that they require extensive computational resources which are not available in environs where electrical machines are most often placed. Additionally, these environments are plagued by noise which considerably affects the quality of input signal i.e., current. Other issues related to on-board system is the associated cost of diagnosis hardware. Concretely, the algorithm for Wavelet Analysis of a signal should be capable of producing reasonable results using cost effective hardware which comes with the compromise of lesser resolution, limited memory and low power consumption. In this proposed work, implementation scheme of Wavelet Transform on low cost PSoC3 hardware is presented which tightly integrates the FPGA blocks and DSP processor on the chip with microcontroller core to yield a fast and robust hardware accelerated mechanism to compute Wavelet Transform, Wavelet thresholding for denoising and classification.
Starting Page	514
Ending Page	518
File Size	1118516
Page Count	5
File Format	PDF
ISBN	9781479957545
e-ISBN	9781479957552
DOI	10.1109/INMIC.2014.7097394
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-12-08
Publisher Place	Pakistan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Wavelet transforms Hardware Support vector machines Noise reduction Computer architecture Noise
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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