NDLI: Performance Modeling of Design Patterns for Distributed Computation

Content Provider	IEEE Xplore Digital Library
Author	Strebelow, R. Tribastone, M. Prehofer, C.
Copyright Year	2012
Abstract	In software engineering, design patterns are commonly used and represent robust solution templates to frequently occurring problems in software design and implementation. In this paper, we consider performance simulation for two design patterns for processing of parallel messaging. We develop continuous-time Markov chain models of two commonly used design patterns, Half-Sync/Half-Async and Leader/Followers, for their performance evaluation in multicore machines. We propose a unified modeling approach which contemplates a detailed description of the application-level logic and abstracts away from operating system calls and complex locking and networking application programming interfaces. By means of a validation study against implementations on a 16-core machine, we show that the models accurately predict peak throughputs and variation trends with increasing concurrency levels for a wide range of message processing workloads. We also discuss the limits of our models when memory-level internal contention is not captured.
Starting Page	251
Ending Page	258
File Size	343641
Page Count	8
File Format	PDF
ISBN	9781467324533
ISSN	15267539
DOI	10.1109/MASCOTS.2012.37
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-08-07
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Message systems Monitoring Instruction sets Unified modeling language Object oriented modeling Sockets Computational modeling multi-core systems Design patterns performance models Half-Sync/ Half-Async Leader/Followers
Content Type	Text
Resource Type	Article

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