NDLI: PUD-LRU: An Erase-Efficient Write Buffer Management Algorithm for Flash Memory SSD

Content Provider	IEEE Xplore Digital Library
Author	Jian Hu Hong Jiang Lei Tian Lei Xu
Copyright Year	2010
Abstract	Flash memory SSDs pose a well-known challenge, that is, the erase-before-write problem. Researchers try to solve this inherent problem from two different angles by either designing sophisticated Flash Translation Layer (FTL) schemes to postpone and minimize erasures or designing flash-aware buffer management algorithms to absorb unnecessary erasures. Our experimental results show that buffer management inside SSD is necessary and indispensable. Further, based on our observation that TPC and some server workloads have strong temporal locality, this paper proposes a new flash-aware write-buffer management algorithm, called PUD-aware LRU algorithm (PUD-LRU), based on the Predicted average Update Distance (PUD) as the key block replacement criterion on top of log-block FTL schemes. The main idea of PUD-LRU is to differentiate blocks and judiciously destage blocks based on their frequency and recency so as to avoid the unnecessary erasures due to repetitive updates. To take advantage of the characteristics of log-block FTL and increase the erase efficiency, PUD-LRU maximizes the number of valid pages in the destaged block in each erase operation. Our trace-driven experimental results show that the PUD-LRU algorithm can reduce the number of erasures of the state-of-the-art buffer management algorithm BPLRU by up to 42%, and average response time by up to 56%, while reducing the two measures of the state-of-the-art page-mapping FTL scheme DFTL by up to 73% and 75%, respectively.
Starting Page	69
Ending Page	78
File Size	1713835
Page Count	10
File Format	PDF
ISBN	9781424481811
ISSN	15267539
DOI	10.1109/MASCOTS.2010.16
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-08-17
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Random access memory Ash Algorithm design and analysis Prediction algorithms Servers Equations Radiation detectors
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
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3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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