NDLI: An all digital 650-Mbps demonstration receiver for NASA's high data rate satellite applications

Content Provider	IEEE Xplore Digital Library
Author	Thompson, M. Jones, W.
Copyright Year	1992
Description	Author affiliation: Interstate Electron. Corp., Anaheim, CA, USA (Thompson, M.; Jones, W.)
Abstract	A demonstration receiver that tracks and demodulates 650-Mb/s QPSK (quadrature phase-shift keying) data has been developed, utilizing a parallel processing VLSI architecture and multirate digital signal processing, to meet upcoming NASA satellite communication requirements. Data rates of 650 Mb/s were achieved with low implementation loss and two-sample/symbol operation using high-speed digital GaAs logic in the front and back end, with the majority of the computationally intensive signal processing implemented in CMOS VLSI. Using a parallel architecture combined with multirate digital signal processing means that receiver speed is no longer limited to the speed of the signal processing hardware elements, but only by the speed of the analog-to-digital converters. In addition to unsurpassed data rate levels, superior bit error rate (BER) performance has been achieved using a joint feedforward and feedback timing estimator and data recovery algorithm. Laboratory performance results for the hardware demonstration receiver are presented as well as a detailed discussion of the hardware implementation and signal processing algorithms.
Starting Page	194
Ending Page	198
File Size	669138
Page Count	5
File Format	PDF
ISBN	078030585X
DOI	10.1109/MILCOM.1992.244166
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1992-10-11
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Digital signal processing Signal processing algorithms Hardware Very large scale integration Bit error rate Quadrature phase shift keying Phase shift keying Parallel processing Computer architecture NASA
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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