NDLI: Hardware-efficient encryption encoder and decoder unit

Content Provider	IEEE Xplore Digital Library
Author	Adamo, O. Shengli Fu Varanasi, M.
Copyright Year	2008
Description	Author affiliation: Comput. Sci. & Eng., Univ. of North Texas, Denton, TX (Adamo, O.) \|\| Electr. Eng., Univ. of North Texas, Denton, TX (Shengli Fu; Varanasi, M.)
Abstract	The distribution and retrieval of multimedia data over wireless networks have become widespread, thus creating the need for secure transmission of data over networks. However, one of the main problems with the secure transmission of digital data over wireless networks is that the errors that occur during transmission typically need to be resolved before decryption can begin. Because of the limited resources such as power and size of these wireless devices, hardware-efficient implementations of these operations are essential. This paper presents a joint hardware-efficient design for both encryption and channel coding that is optimized for low-resource requirements. We implemented the Rijndael advance encryption standard (AES) algorithm and convolutional encoder for the encryption and encoder sub-unit, respectively. In order to decode the received digital data, we use the Viterbi decoder, which has been known to be suited for convolutional codes. Our design has a 70% reduction in the number of hardware resources for the encoding sub-unit through the block of XORs. The low-resource usage is achieved through an integrated architecture of the encoding units. Most of the hardware reduction was achieved in the AddRoundKey and the encoder sub-unit. Our system was implemented on a Xilinx Spartan 3 xc3s200FT256 using ISE foundation 8.1, and 13% of the slices were used for the Viterbi decoder with 674 bels. The maximum frequency was 55.872 MHz with a minimum period of 17.898 ns.
Starting Page	1
Ending Page	6
File Size	2314683
Page Count	6
File Format	PDF
ISBN	9781424426768
DOI	10.1109/MILCOM.2008.4753190
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-11-16
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Cryptography Decoding Wireless networks Convolutional codes Viterbi algorithm Hardware Information retrieval Communication system security Channel coding Design optimization
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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