NDLI: Design planning for single chip implementation of digital wireless mobile transceiver

Content Provider	IEEE Xplore Digital Library
Author	Sahula, V. Ravikumar, C.P.
Copyright Year	2000
Description	Author affiliation: Dept. of Electron. & Comm. Eng., Regional Eng. Coll., Jaipur, India (Sahula, V.)
Abstract	In this paper, we present a design planning paradigm for the design of a wireless mobile transceiver. We consider the digital part in a single chip implementation of a transceiver based on the CDMA spread spectrum technique. The complexity of such a chip implementation makes the design process complex and very expensive. The desired characteristics of a mobile transceiver are low cost, small size, and low power. Design cost forms a major portion of total system cost. In order to reduce design cost, design completion time should be reduced. We assume hardware-software design flow for design of the transceiver. We analyze the design flow using the hierarchical concurrent flow graph (HCFG) approach. We illustrate, using AND and OR concurrent constructs of the HCFG approach, how the design process completion time can be reduced by employing concurrent design efforts. We also present an approach for completion time improvement which considers the sensitivity of completion time with respect to task completion time and probabilities. HCFG analysis facilitates a pre-execution "what-if" analysis to determine the suitable design flow which provides lowest process completion time.
Starting Page	19
Ending Page	23
File Size	453833
Page Count	5
File Format	PDF
ISBN	0780358937
DOI	10.1109/ICPWC.2000.905765
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2000-12-17
Publisher Place	India
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Transceivers Process design Costs Flow graphs Consumer electronics Design engineering Time to market Design optimization Educational institutions Multiaccess communication
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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