NDLI: Performance evaluation of a DySER FPGA prototype system spanning the compiler, microarchitecture, and hardware implementation

Content Provider	IEEE Xplore Digital Library
Author	Chen-Han Hoy Govindarajuz, V. Nowatzki, T. Nagaraju, R. Marzecy, Z. Agarwal, P. Frericks, C. Cofell, R. Sankaralingam, K.
Copyright Year	2015
Description	Author affiliation: ARM, Univ. of Wisconsin, Madison, WI, USA (Nagaraju, R.) \|\| Intel, Univ. of Wisconsin, Madison, WI, USA (Agarwal, P.) \|\| Oracle, Univ. of Wisconsin, Madison, WI, USA (Govindarajuz, V.) \|\| Univ. of Wisconsin, Madison, WI, USA (Nowatzki, T.; Cofell, R.; Sankaralingam, K.) \|\| Samsung, Univ. of Wisconsin, Madison, WI, USA (Frericks, C.) \|\| Qualcomm, Univ. of Wisconsin, Madison, WI, USA (Chen-Han Hoy; Marzecy, Z.)
Abstract	Specialization and accelerators are being proposed as an effective way to address the slowdown of Dennard scaling. DySER is one such accelerator, which dynamically synthesizes large compound functional units to match program regions, using a co-designed compiler and microarchitecture. We have completed a full prototype implementation of DySER integrated into the OpenSPARC processor (called SPARC-DySER), a co-designed compiler in LLVM, and a detailed performance evaluation on an FPGA system, which runs an Ubuntu Linux distribution and full applications. Through the prototype, this paper evaluates the fundamental principles of DySER acceleration. Our two key findings are: i) the DySER execution model and microarchitecture provides energy efficient speedups and the integration of DySER does not introduce overheads - overall, DySER's performance improvement to OpenSPARC is 6X, consuming only 200mW ; ii) on the compiler side, the DySER compiler is effective at extracting computationally intensive regular and irregular code. For non-computationally intense irregular code, two control flow shapes curtail the compiler's effectiveness, and we identify potential adaptive mechanisms. Finally, our experience of bringing up an end-to-end prototype of an ISA-exposed accelerator has made clear that two particular artifacts are greatly needed to perform this type of design more quickly and effectively: 1) Open-source implementations of high-performance baseline processors, and 2) Declarative tools for quickly specifying combinations of known compiler transforms.
Sponsorship	IEEE Comput. Soc.
Starting Page	203
Ending Page	214
File Size	2777209
Page Count	12
File Format	PDF
ISBN	9781479919574
DOI	10.1109/ISPASS.2015.7095806
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2015-03-29
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Field programmable gate arrays Benchmark testing Prototypes Performance evaluation Microarchitecture Acceleration Computer architecture
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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