NDLI: High-level performance modeling of task-based algorithms

Content Provider	IEEE Xplore Digital Library
Author	Alexandrov, A. Armstrong, D. Rajic, H. Voss, M. Hayes, D.
Copyright Year	2010
Description	Author affiliation: Performance, Analysis and Threading Lab, Intel Corporation, USA (Alexandrov, A.; Armstrong, D.; Rajic, H.; Voss, M.)
Abstract	Performing modeling and visualization of task-based parallel algorithms is challenging. Libraries such as Intel Threading Building Blocks (TBB) and Microsoft's Parallel Patterns Library provide high-level algorithms that are implemented using low-level tasks. Current tools present performance at this lower level. Developers like to tune and debug at the same level as the coding abstraction, so in this paper we propose tools and a two step methodology that target this level of abstraction. In the first step, the system level metrics of utilization and overhead are collected to determine if performance is acceptable. If a problem is suspected, the second step of our methodology projects these metrics on to the algorithms contained in the application. Using these projections many common performance issues can be quickly diagnosed. We demonstrate our methodology using a prototype implementation that is integrated with the Intel Threading Building Blocks library. We show the flexibility of the approach by analyzing three applications, including a client-server benchmark that uses a parallel_for nested within a parallel pipeline.
Starting Page	184
Ending Page	193
File Size	1163274
Page Count	10
File Format	PDF
ISBN	9781424460236
e-ISBN	9781424460243
DOI	10.1109/ISPASS.2010.5452025
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-03-28
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Performance analysis Parallel algorithms Algorithm design and analysis Visualization Prototypes Pipelines Runtime library Parallel programming Measurement parallel programming tools Intel^® Threading Building Blocks task-based algorithms
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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