NDLI: The BlueGene/L pseudo cycle-accurate simulator

Content Provider	IEEE Xplore Digital Library
Author	Bachega, L.R. Brunheroto, J.R. DeRose, L. Mindlin, P. Moreira, J.E.
Copyright Year	2004
Description	Author affiliation: Thomas J. Watson Res. Center, IBM, Yorktown Heights, NY, USA (Bachega, L.R.; Brunheroto, J.R.; DeRose, L.; Mindlin, P.; Moreira, J.E.)
Abstract	The design and development of a new computer system is a lengthy process, with a considerable amount of time elapsed between the beginning of development and first hardware availability. Hence, fast and reasonably accurate simulation of processor architecture has become critical as an enabling mechanism for software engineers to develop and tune system software and applications. In this paper, we present the time-stamped timing model extensions to the BlueGene/L functional simulator. These extensions were implemented to create a pseudo cycle-accurate simulator capable of providing tracing capabilities for detection of bottlenecks and for performance tuning of applications, before the actual hardware became available. Our validation tests, using the DAXPY kernel and the serial version of the NAS benchmarks, show that our pseudo cycle-accurate simulator provides timing information within 15% of the times measured using the actual BlueGene/L hardware. In addition, we present a couple of case studies, which describes how this simulator can be used for identification of performance bottlenecks and for application tuning.
Sponsorship	IEEE Comput. Soc
Starting Page	36
Ending Page	44
File Size	576142
Page Count	9
File Format	PDF
ISBN	0780383850
DOI	10.1109/ISPASS.2004.1291354
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2004-03-10
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Computational modeling Hardware Application software Timing Analytical models System software Testing Kernel Supercomputers Computer architecture
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Data cache prefetching design space exploration for BlueGene/L supercomputer

Flight Simulator Architecture Development and Implementation

BZK.SAU: Implementing a hardware and software-based Computer Architecture simulator for educational purpose

ATTILA: a cycle-level execution-driven simulator for modern GPU architectures

Modeling application performance by convolving machine signatures with application profiles

Flow: A Stream Processing System Simulator

FPGA-Accelerated Simulation Technologies (FAST): Fast, Full-System, Cycle-Accurate Simulators

Simulating A Complex Software System

Fast, flexible, cycle-accurate energy estimation

The BlueGene/L pseudo cycle-accurate simulator

Similar Documents

Data cache prefetching design space exploration for BlueGene/L supercomputer

Flight Simulator Architecture Development and Implementation

BZK.SAU: Implementing a hardware and software-based Computer Architecture simulator for educational purpose

ATTILA: a cycle-level execution-driven simulator for modern GPU architectures

Modeling application performance by convolving machine signatures with application profiles

Flow: A Stream Processing System Simulator

FPGA-Accelerated Simulation Technologies (FAST): Fast, Full-System, Cycle-Accurate Simulators

Simulating A Complex Software System

Fast, flexible, cycle-accurate energy estimation

The BlueGene/L pseudo cycle-accurate simulator