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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Kryszczuk, K. Hurley, P. Sayah, R. |
| Copyright Year | 2010 |
| Abstract | Full-chip printability simulations for VLSI layouts use analytical and heuristic physical process models, and require an explicit creation of a mask and image. This is a computationally expensive task, often prohibitively so, especially when prototyping new designs. In this paper we show that using orthogonal transform-based fixed-length feature vector representations of 22nm VLSI layouts to perform classification based rapid printability prediction, can help in avoiding or reducing the number of simulations. Furthermore, in order to overcome the problem of scarcity of training data, we show how re-scaled, abundant 45nm designs can train error prediction models for new, native 22nm designs. Our experiments, run on M1 layer data and line width errors, demonstrate the viability of the proposed approach. |
| Starting Page | 2764 |
| Ending Page | 2767 |
| File Size | 551092 |
| Page Count | 4 |
| File Format | |
| ISBN | 9781424475421 |
| ISSN | 10514651 |
| e-ISBN | 9781424475414 |
| DOI | 10.1109/ICPR.2010.677 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2010-08-23 |
| Publisher Place | Turkey |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Layout Discrete cosine transforms Tiles Training Feature extraction Computational modeling computational lithography VLSI printability prediction |
| Content Type | Text |
| Resource Type | Article |
| Subject | Computer Vision and Pattern Recognition |
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