NDLI: A sliding memory array processor for low level vision

Content Provider	IEEE Xplore Digital Library
Author	Sunwoo, M.H. Aggarwal, J.K.
Copyright Year	1990
Description	Author affiliation: Comput. & Vision Res. Center, Texas Univ., Austin, TX, USA (Sunwoo, M.H.; Aggarwal, J.K.)
Abstract	A mesh-connected architecture, called a Sliding Memory Plane (SliM) array processor, for low-level vision tasks is described. SliM alleviates several disadvantages of existing mesh-connected architectures. It is a fine-grained massively parallel single-instruction multiple-data architecture. The inter-PE communication can occur without interrupting PEs. Two I/O planes can provide a buffering capability. The communication and I/O overheads can each be overlapped with the computation, and both are therefore greatly diminished. Bit-serial communication and bit-parallel computation are used. Various types of communication and virtual interconnections for communication between diagonal-direction PEs are provided. Each PE can operate separately, based on some degree of local autonomy. SliM shows thorough applicability with these configurations. Parallel algorithms for low-level vision tasks on SliM having a zero or an O(1) communication complexity are proposed. The performance of SliM is illustrated with several examples of low-level computer vision tasks.
Starting Page	312
Ending Page	317
File Size	620445
Page Count	6
File Format	PDF
ISBN	0818620625
DOI	10.1109/ICPR.1990.119375
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1990-06-16
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Computer architecture Computer vision Degradation Topology Parallel algorithms Concurrent computing Digital audio players Hypercubes Head Logic circuits
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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